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Testing MSP430

Comparing Cost and Benefits of

Vector vs. Vectorless

There are 396 unique devices in this family of microcontrollers. You can access documentation for these microcontrollers at the ULR below. A DTS for these parts cannot be generated with BasicScantm because these devices have JTAG but no Boundary Scan cells designed into the part. BSDL files are not available.


This comparison shows the MSP430F147 device as an example. As you can see by the comparison below, a vector based model provides far better test coverage, that is more reliable, for a fraction of the cost.  Yet most test engineers still choose Vectorless Test because that's the Industry Standard.



MSP430F147 Using FrameScantm

(Industry Standard)



MSPP430F147 Using MSP430Scan

(Vector Based Test provided by Uwharrie Test Solutions)


  • FrameScan Module                                                              $580.00

  • FrameScan Probe for one device                                            $30.00

  • Fixture Installation        (Fixture Supplier estimate)                  $500.00

  • Total Recurring cost per fixture                                      $1120.00

  • One-time license fee for every Test Station or GR228X      $10000.00



  • DTS Plug & Play (48 GPIOs at $10/GPIO)                                        $480

  • No special License Fee                                                                           $0

  • Recurring cost per fixture                                                                   $0

  • A utility that can generate a DTS for any MSP430FXXXX               $3000



Test Coverage

  • Connectivity of signal pins to PCB

Test Coverage

  • Connectivity of signal pins to PCB

  • Stuck-at coverage of all drivable GPIOs as inputs 1/0

  • Verifies that device functions when powered

  • Device ID

  • Boot Strap Loader Version

  • Pins with no probe access pulled-up, pulled-down or open are still testable for a single state.

  • No-access pins driven by other devices are still testable through clustered logic.


Design for Testability Requirement
  • Probe access to tested pins

Design for Testability Requirement
  • Probe access to JTAG and RESET

  • Pins with probe access are tested H/L



  • Reliability issues with probe placement wear and tear, lot code changes, false fail, false pass etc...
  • Test time estimate 100M sec

Other Advantages

  • No unnecessary fixture hardware to wear out and replace

  • Burst Duration only 2.04474M sec



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