Uwharrie Test Solutions

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Design for Testability

Successful vector test is contingent on responsible DFT.

If you are inquiring about a specific device that you want to ISP or vector test, I will give you DFT guidelines about that device. In most cases this will be free of charge, regardless of whether or not you purchase my services.

You may also contact me for a formal DFT review.

Seven Misconceptions about ICT Design for Testability

I don't need a DFT review my CAD program automatically checks my boards.

Not so fast. A utility built into a CAD program can only check for things like probe access and adequate spacing of access points. And sometimes it misses probe access locations that are buried under solder mask and component bodies. Even if you have access to every net, your electrical DFT can still be a disaster. DFT for In-Circuit Test must also include the ability isolate the devices that you need to test.

My design isn't using it, I can tie it off.

Beware, if the pin has a logical name like TEST, SLEEP, HIZ, SHDN or OE, tying it off is probably a bad idea. Connect it through a pull-up or pull-down and provide access to the pin.

Unused SMT pins don't need probe access.

In most cases they don't. But first make sure this is not a pin that is part of the testability of the device. I have seen board designers leave off JTAG ports this way. Sometimes these unused pins are the outputs of NAND Trees. Understand what the pins does before you write-off the need for an access point.

I don't provide access to a couple of pins, that's just a couple of pins not tested.

Bad assumption. For a non Boundary-Scan device, just one pin can render an entire part untestable, as well as devices around it. Examples of this, a control or address line of a memory, an -OE for a data driver. Inputs are worse than outputs or bi-directionals.

DFT only goes down to the PCB level, when your board is testable it's testable.

Not correct. Chip designers need to be aware of design for testability as well. I have seen PGAs and FPGAs, where the designer of the logic managed to program the part in a way that broke the Boundary-Scan. I have seen pre programmed gate arrays that did not provide any means to disable their buses, rendering everything around them untestable.

My board has Boundary-Scan, I don't need probe access.

This is only the case for nets that have interconnections to all Boundary-Scan compliant devices. There are certain tricks that board edge JTAG can do to write and read non- compliant memories with no access, or so they say. I would like to see them do it with a non-compliant SDRAM. A Boundary-Scan part can write a pattern to a non-compliant latch. But, if you don't have probe access to the other side of the latch, or another compliant part to read it from, you're out of luck. There are new techniques that will toggle a no access pin via a Boundary-Scan part and pick up the signal on a FrameScan probe. Still, I remain somewhat skeptical about this Voodoo. Perhaps it works to a degree. But the fact remains, the less you access, the less you test, and the less precise your diagnostics will be. You cannot blindly leave out probe access if you expect to test. You still have to strategically decide what needs access and what does not.

All probe access points are created equal.

This is the one that is the most difficult to catch. It only applies to high speed critical signals, mostly clock signals with long runs across the board. In a situation like this, the probe access location should always be positioned as far away from the critical DUTs as possible. Otherwise the signal at the DUT is subject line reflection and double clocks. A probe in the wrong place can wreak havoc on clock inputs to serial flash, SDRAMs, Microcontroller and TCK for high speed JTAG. Sometimes you can band-aid the problem with different slew rates, series resistors in the fixture, or slowing down the test. I recommend finding this problem and fixing it before it bites you.

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